|
ECS 50 |
CUSP Crib Sheet |
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Data
Transfer Instructions |
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|
Mnemonic |
Opcode |
Flags |
Address
Mode Times |
Behavior |
Mnemonic |
||||||
|
OV |
EQ |
LT |
IE |
None |
0/1 |
2/3/4/5 |
6/7/8/9 |
||||
|
LDA
xxx |
00 |
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|
|
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|
2 |
3 |
4 |
ACC = operand |
LDA
xxx |
|
LDX
xxx |
01 |
1 |
|
|
|
|
2 |
3 |
4 |
XR = operand |
LDX
xxx |
|
LDS
xxx |
02 |
1 |
|
|
|
|
2 |
3 |
4 |
SP = operand |
LDS
xxx |
|
LDF
xxx |
03 |
1 |
|
|
|
|
2 |
3 |
4 |
FP = operand |
LDF
xxx |
|
STA
xxx |
04 |
|
|
|
|
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|
3 |
4 |
M[opaddr]
= ACC |
STA
xxx |
|
STX
xxx |
05 |
|
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|
3 |
4 |
M[opaddr]
= XR |
STX
xxx |
|
STS
xxx |
06 |
|
|
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|
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|
3 |
4 |
M[opaddr]
= SP |
STS
xxx |
|
STF
xxx |
07 |
|
|
|
|
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|
3 |
4 |
M[opaddr]
= FP |
STF
xxx |
|
PSH
xxx |
08 |
|
|
|
|
|
3 |
4 |
5 |
M[--SP]= operand |
PSH
xxx |
|
POP
xxx |
09 |
|
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|
4 |
5 |
M[opaddr]
= M[SP++] |
POP
xxx |
|
CLR
xxx |
0A |
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|
3 |
4 |
M[opaddr]
= $000000 |
CLR
xxx |
|
SET
xxx |
0B |
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|
|
|
|
3 |
4 |
M[opaddr]
= $FFFFFF |
SET
xxx |
|
TAX |
FFF000 |
1 |
|
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|
2 |
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|
|
XR = ACC |
TAX |
|
TAS |
FFF001 |
1 |
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|
2 |
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SP = ACC |
TAS |
|
TAF |
FFF002 |
1 |
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|
2 |
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FP = ACC |
TAF |
|
TXA |
FFF003 |
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2 |
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ACC = XR |
TXA |
|
TXS |
FFF004 |
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2 |
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SP = XR |
TXS |
|
TXF |
FFF005 |
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|
2 |
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FP = XR |
TXF |
|
TSA |
FFF006 |
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|
2 |
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ACC = SP |
TSA |
|
TSX |
FFF007 |
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2 |
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XR = SP |
TSX |
|
TSF |
FFF008 |
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2 |
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FP = SP |
TSF |
|
TFA |
FFF009 |
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2 |
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ACC = FP |
TFA |
|
TFX |
FFF010 |
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2 |
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XR = FP |
TFX |
|
TFS |
FFF011 |
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2 |
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SP = FP |
TFS |
|
PSHA |
FFF012 |
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|
3 |
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M[--SP] = ACC |
PSHA |
|
PSHX |
FFF013 |
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|
3 |
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M[--SP] = XR |
PSHX |
|
PSHF |
FFF014 |
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|
3 |
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M[--SP] = FP |
PSHF |
|
POPA |
FFF015 |
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|
3 |
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ACC = M[SP++] |
POPA |
|
POPX |
FFF016 |
1 |
|
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|
3 |
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XR = M[SP++] |
POPX |
|
POPF |
FFF017 |
1 |
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|
3 |
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FP = M[SP++] |
POPF |
|
Arithmetic
Instructions |
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|
Mnemonic |
Opcode |
OV |
EQ |
LT |
IE |
None |
0/1 |
2/3/4/5 |
6/7/8/9 |
Behavior |
Mnemonic |
|
|
10 |
1 |
2 |
3 |
|
|
2 |
3 |
4 |
ACC += operand |
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|
ADX
xxx |
11 |
1 |
2 |
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|
|
2 |
3 |
4 |
XR += operand |
ADX
xxx |
|
ADS
xxx |
12 |
1 |
2 |
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|
|
2 |
3 |
4 |
SP += operand |
ADS
xxx |
|
ADF
xxx |
13 |
1 |
2 |
|
|
|
2 |
3 |
4 |
FR += operand |
ADF
xxx |
|
SBA
xxx |
14 |
1 |
2 |
3 |
|
|
2 |
3 |
4 |
ACC -= operand |
SBA
xxx |
|
SBX
xxx |
15 |
1 |
2 |
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|
2 |
3 |
4 |
XR -= operand |
SBX
xxx |
|
SBS
xxx |
16 |
1 |
2 |
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|
2 |
3 |
4 |
SP -= operand |
SBS
xxx |
|
SBF
xxx |
17 |
1 |
2 |
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|
2 |
3 |
4 |
FP -= operand |
SBF
xxx |
|
MUL
xxx |
18 |
1 |
2 |
3 |
|
|
4 |
5 |
6 |
ACC *= operand |
MUL
xxx |
|
DIV
xxx |
19 |
1 |
2 |
3 |
|
|
4 |
5 |
6 |
ACC /= operand |
DIV
xxx |
|
MOD
xxx |
1A |
1 |
2 |
3 |
|
|
4 |
5 |
6 |
ACC %= operand |
MOD
xxx |
|
INC
xxx |
1B |
1 |
2 |
3 |
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|
5 |
6 |
M[operand]++ |
INC
xxx |
|
DEC
xxx |
1C |
1 |
2 |
3 |
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|
5 |
6 |
M[operand]-- |
DEC
xxx |
|
NEG
xxx |
1D |
1 |
2 |
3 |
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|
5 |
6 |
M[operand] = -M[operand] |
NEG
xxx |
|
NEGA |
FFF020 |
1 |
2 |
3 |
|
2 |
|
|
|
ACC = -ACC |
NEGA |
Flag notes: 1. OV = overflow occurred; 2. EQ = (result == 0); 3. LT = (result < 0).
Comparison
Instructions |
|||||||||||
|
Mnemonic |
Opcode |
Flags |
Address
Mode Times |
Behavior |
Mnemonic |
||||||
|
OV |
EQ |
LT |
IE |
None |
0/1 |
2/3/4/5 |
6/7/8/9 |
||||
|
CMA
xxx |
20 |
|
4 |
5 |
|
|
2 |
3 |
4 |
ACC – operand |
CMA
xxx |
|
CMX
xxx |
21 |
|
4 |
5 |
|
|
2 |
3 |
4 |
XR – operand |
CMX
xxx |
|
CMS
xxx |
22 |
|
4 |
5 |
|
|
2 |
3 |
4 |
SP – operand |
CMS
xxx |
|
CMF
xxx |
23 |
|
4 |
5 |
|
|
2 |
3 |
4 |
FP – operand |
CMF
xxx |
|
TST
xxx |
24 |
|
6 |
7 |
|
|
2 |
3 |
4 |
operand – $0 |
TST
xxx |
|
Logical
(Bit) Instructions |
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|
AND
xxx |
30 |
|
2 |
3 |
|
|
2 |
3 |
4 |
ACC &= operand |
AND
xxx |
|
OR
xxx |
31 |
|
2 |
3 |
|
|
2 |
3 |
4 |
ACC |= operand |
OR
xxx |
|
XOR
xxx |
32 |
|
2 |
3 |
|
|
2 |
3 |
4 |
ACC ^= operand |
XOR
xxx |
|
COM
xxx |
33 |
|
2 |
3 |
|
|
|
5 |
6 |
M[operand] = ~M[operand] |
COM
xxx |
|
COMA |
FFF021 |
|
2 |
3 |
|
2 |
|
|
|
ACC = ~ACC |
COMA |
|
SHRA |
FFF022 |
8 |
2 |
3 |
|
2 |
|
|
|
ACC >>= 1 |
SHRA |
|
SHLA |
FFF023 |
9 |
2 |
3 |
|
2 |
|
|
|
ACC <<= 1 |
SHLA |
|
RTRA |
FFF024 |
|
2 |
3 |
|
2 |
|
|
|
ACC rotated right |
RTRA |
|
RTLA |
FFF025 |
|
2 |
3 |
|
2 |
|
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|
ACC rotated left |
RTLA |
|
RROA |
FFF026 |
8 |
2 |
3 |
|
2 |
|
|
|
ACC rotated right, w/OV |
RROA |
|
RLOA |
FFF027 |
9 |
2 |
3 |
|
2 |
|
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|
ACC rotated left, w/OV |
RLOA |
|
Jump
Instructions |
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|
JMP
xxx |
40 |
|
|
|
|
|
|
2 |
3 |
PC = operand |
JMP
xxx |
|
JSR
xxx |
41 |
|
|
|
|
|
|
3 |
4 |
push PC, PC = operand |
JSR
xxx |
|
INT
xxx |
42 |
|
|
|
10 |
|
|
3 |
4 |
push PC+flags,
PC= operand |
INT
xxx |
|
RTN |
FFF040 |
|
|
|
|
3 |
|
|
|
PC = pop |
RTN |
|
IRTN |
FFF041 |
11 |
11 |
11 |
11 |
3 |
|
|
|
PC+flags = pop |
IRTN |
|
JEQ
xxx |
48 |
|
|
|
|
|
|
2 |
3 |
if (EQ == 1) PC = operand |
JEQ
xxx |
|
JNE
xxx |
49 |
|
|
|
|
|
|
2 |
3 |
if (EQ == 0) PC = operand |
JNE
xxx |
|
JLT
xxx |
4A |
|
|
|
|
|
|
2 |
3 |
if (LT == 1) PC = operand |
JLT
xxx |
|
JGE
xxx |
4B |
|
|
|
|
|
|
2 |
3 |
if (LT = 0) PC = operand |
JGE
xxx |
|
JLE
xxx |
4C |
|
|
|
|
|
|
2 |
3 |
if (LT == 1 || EQ == 1) |
JLE
xxx |
|
JGT
xxx |
4D |
|
|
|
|
|
|
2 |
3 |
if (LT = 0 && EQ =
0) |
JGT
xxx |
|
JOV
xxx |
4E |
|
|
|
|
|
|
2 |
3 |
if (OV == 1) PC = operand |
JOV
xxx |
|
JNO
xxx |
4F |
|
|
|
|
|
|
2 |
3 |
if (OV == 0) PC = operand |
JNO
xxx |
|
Character,
Looping, Subroutine, I/O, Miscellaneous Instructions |
|||||||||||
|
Mnemonic |
Opcode |
OV |
EQ |
LT |
IE |
None |
0/1 |
2/3/4/5 |
6/7/8/9 |
Behavior |
Mnemonic |
|
LDC
xxx |
50 |
|
12 |
|
|
|
|
3 |
4 |
ACC = $FF & M[opaddr][XR] |
LDC
xxx |
|
STC
xxx |
51 |
|
|
|
|
|
|
4 |
5 |
M[opaddr][XR]
= ACC & $FF |
STC
xxx |
|
AOC
xxx |
60 |
13 |
14 |
15 |
16 |
|
2 |
3 |
4 |
++XR – operand |
AOC
xxx |
|
SOJ
xxx |
61 |
13 |
|
|
|
|
|
3 |
4 |
if (--XR >= 0) PC =
operand |
SOJ
xxx |
|
BGN
xxx |
68 |
|
|
|
|
|
3 |
4 |
5 |
push FP; SP -= operand; FP =
SP |
BGN
xxx |
|
FIN
xxx |
69 |
|
|
|
|
|
3 |
4 |
5 |
SP += operand; FP = pop |
FIN
xxx |
|
INB
xxx |
70 |
|
12 |
21 |
|
|
|
3 |
4 |
ACC = $FF & Port[opaddr] |
INB
xxx |
|
OUTB
xxx |
71 |
|
|
|
|
|
|
3 |
4 |
Port[opaddr]
= ACC & $FF |
OUTB
xxx |
|
INW
xxx |
70 |
|
12 |
18 |
|
|
|
5 |
6 |
ACC = Port[oppadr..oppadr + 2] |
INW
xxx |
|
OUTW
xxx |
71 |
|
|
|
|
|
|
5 |
6 |
Port[oppadr..oppadr + 2] = ACC |
OUTW
xxx |
|
SIE |
FFF032 |
|
|
|
19 |
2 |
|
|
|
IE = 1 |
SIE |
|
CIE |
FFF033 |
|
|
|
20 |
2 |
|
|
|
IE = 0 |
CIE |
|
NOP |
FFF038 |
|
|
|
|
2 |
|
|
|
None |
NOP |
|
HLT |
FFFFFF |
|
|
|
|
2 |
|
|
|
machine halts |
HLT |
Flag notes: 1. OV = overflow
occurred; 2. EQ = (result == 0); 3. LT = (result < 0). 4. EQ = (register == operand),
5. LT = (register <
operand), 6. EQ = (operand ==
0), 7. LT = (operand < 0), 8. OV = LSB of ACC,
9. OV = MSB of ACC, 10. IE = 0, 11. All flags restored to values saved on stack, 12. EQ = (ACC == 0),
13. OV = (overflow in updated
XR), 14. EQ = (updated XR ==
operand), 15. LT = (updated XR <
operand),
16. EQ = (updated XR == 0), 17. LT = (MSB of Port == 0) 18. LT = (ACC < 0), 19. IE = 1, 20. IE = 0
21. LT = (leftmost bit of
port)